1. Field of the Invention
The subject invention relates generally to synchronous digital systems and more particularly to an improved method and apparatus for clock generation in such systems.
2. Description of Related Art
A synchronous digital system is defined as having a single clock signal to which all activity in the system is synchronized. This signal is presently routed on metal wires throughout the system in much the same manner as every other signal in that system. Since the clock signal must go to every sequential element in the system, a very large and complex network results. The parasitics that this large network encounters cause delays in distribution of the clock signal, called clock skew. The maximum clock skew is subtracted from the clock period thus reducing the time budget for logic between sequential elements.
Typically, in the prior art, clock frequencies have been kept low enough that the skew component is small compared to total clock period. Another common practice is to over-constrain the combinatorial logic between sequential elements to be "safe" for any possible clock skew that may be produced for any particular routing of the clock network. Another approach which has been used is to employ phase lock loops to resynchronize clocks at various points a chip. Another approach that is seen in today's in desk top PC's is to run the processor chip at a higher frequency than the rest of the system, but phase locked to the lower system clock rate. One of the reasons for this approach is that high speed clock distribution over anything but the shortest distances (e.g. intrachip) is exceedingly difficult.
Early research was also done into distributing clocks by fiber optics, but such an approach has appeared impractical due to the complex problems presented by the necessity to mix materials in order to create a large and complex fiber network in a semi-conductor substrate or chip.
As system clock rates increase in synchronous digital systems and semiconductor fabrication geometries decrease, clock skew becomes a dominant factor in determining master clock frequency and thus maximum system performance. Concomitantly, the prior art approaches to dealing with clock skew become less and less acceptable.